This invention relates to a semiconductor device including a capacitor especially a forming method of the capacitor.
In order to fabricate a high density semiconductor memory device such as a dynamic random access memory (DRAM) device, a storage capacitor must take up less planar area in each memory cell. On the other hand, a sufficiently high charge capacity must be maintained while a storage capacitor is scaled down in dimensions. Efforts to maintain charge capacity have concentrated on building three-dimension capacitor structures that increase a capacitor surface area. One of the three-dimension capacitor structures is referred to as a deep hole capacitor which generally extends significantly above a surface on an underlying substrate in order to provide the capacitor with a large surface area and thus sufficient storage capacity. Such deep-hole capacitor is disclosed in, for example, US 2006/0086961 A1, which is incorporated herein by reference.
As a matter known to the inventor, a hole deeper than 2000 nm has a sidewall on which a bowing shape appears in a plane perpendicular to a substrate. In other words, the deeper hole is formed with a particular vase-shaped profile which has upper and lower sections; the upper section has larger sizes with increased depths, while the lower section has smaller sizes with increased depths. The particular vase-shaped profile leads to problems in the subsequent formation processes, especially, a void or a seam undesirably formed in an upper electrode of a capacitor.